Data processing systems generally include multiple units such as processing units, memory units, input/output units, and the like, which are interconnected over one or more system interfaces. The interfaces provide for the transfer of digital signals between the units. Since many of the operations within data processing systems involve such transfers, the efficiency of the interfaces has a major impact on the overall performance of the data processing system.
Many conventional interfaces used within data processing systems have several types of signal lines, including data lines for transferring data signals, and address lines for transferring address signals. The address lines generally provide information indicative of the type of request, and further indicate a unit and/or a particular addressable resource associated within the unit that is involved with the request. The data lines provide data signals which are associated with the request.
Requests for data transfers may occur at a faster rate than the memory and associated cache coherency logic can sustain. A buffering technique may be used to queue such requests until they can be processed. However, the queuing function can sometimes result in inefficient and discriminatory request servicing. In some cases, one processor's requests may be repeatedly processed, while another's are left relatively unattended. In other cases, a processor having relatively few requests may needlessly tie up system resources by receiving unnecessary request service polls. These situations can reduce available request bandpass, and increase the probability of request stalling or request lockout. To address this issue, the buffering technique may include a priority scheme to output the data transfer requests according to a priority assigned to each of the data transfer requests. One priority scheme known in the art is known as a "fixed" request priority scheme. Each requester is assigned a fixed priority value, and requests are handled according to this associated priority value. Those requests having a high fixed priority value are always handled prior to those having relatively low priority values. Another request priority scheme is referred to as "snap-fixed", where input request activity is continually or periodically polled. This results in a captured "snapshot" of the request activity at a given time. All of the captured requests are processed in a fixed order until all requests in the snapshot have been processed, at which time a new snapshot is taken. A "simple rotational" priority scheme involves changing the requester priority on a periodic basis. For example, the requester priority may be changed whenever a request is granted priority. Requester (N-1) moves to priority level (N), requester (N) moves to (N+1), and so forth.
Regardless of the priority scheme used, there may be times when the implemented priority scheme inhibits execution of a desired system operation. For example, testing of a complex multiprocessing system having multiple data transfer sources and multiple data transfer destinations can be incredibly complicated, particularly where test programs must be written to simulate transaction "stress" situations. Such a transaction stress situation may occur during normal operation where some resources, like memory, are suddenly inundated with pending data transfer requests. When this occurs, memory response times may be reduced, causing the data transaction queues to fill. The requesting modules must be able to accommodate this situation to avoid queue overrun problems, and it is therefore important to be able to simulate and test these conditions. Further, the memory resources must be able to manage and absorb the high volume of sudden request traffic and properly respond to the requesting modules. Again, these situations require thorough testing.
In order to prepare test programs to simulate these stress conditions, a detailed knowledge of the entire hardware implementation would be required in order to predict the direct effect on system hardware produced by test program stimulus. The time, required resources, complexity and cost of preparing such test programs is prohibitive.
It would therefore be desirable to provide an efficient arrangement and method that allows data transfer request queues to be controlled, or "throttled", by way of simple user-defined parameters. Implemented priority schemes can be maintained, but can be selectively bypassed to perform stress tests, or to accommodate peculiar situations which might arise during normal operation. The present invention provides such a solution, and provides these and other advantages and benefits over the prior art.